SIGNAL DESCRIPTIONS OF 8086

 SIGNAL DESCRIPTIONS OF 8086
 The microprocessor 8086 is a 16-bit CPU available in three clock rates, i.e. 5, 8 and 10 MHz, packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configurations to achieve high performance.  Some of the pins serve a particular function in minimum mode (single processor mode) and others function in maximum mode (multiprocessor mode) configuration. The 8086 signals can be categorized in three groups. The first are the signals having common functions in minimum as well as maximum mode, the second are the signals which have special functions for ·minimum mode and the third are the signals having special functions for maximum mode.The following signal descriptions are common for both the minimum and maximum modes: AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is a wait state. These lines are active high and enter into high impedance state (float to a tristate) during interrupt acknowledge and local bus hold acknowledge cycles.A19-A16/S6-S3: These are the time multiplexed address and status lines. During T1, these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations; status information is available on those lines for T2, T3, Tw and T4. The S4 and S3 pins indicate which segment registers is represently being used for memory accesses . These lines enter into high impedance state (float to a tristate) during the local bus hold acknowledge. The status line S6 is always low (logical). The address bits are separated from the status bits using latches controlled by the ale signal.

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