PROTECTED MODE OF 80386

All the capabilities of 80386 are available for utilization in its protected mode of operation. In protected mode, it can address 4 Gigabytes of physical memory and 64 Terabytes of virtual memory per task.The 80386 in protected mode supports all the software’s (programs) written for 80286 and 8086 to be executed under the control of memory management and protection abilities of 80386.The 80386 in protected mode supports all the software’s (programs) written for 80286 and 8086 to be executed under the control of memory management and protection abilities of 80386.In this mode, the contents of segment registers are used as selectors to address descriptors which contain the segment limit, base address and access rights byte of the segment. The effective address (offset) is added with segment base address to calculate linear address. This linear address is further used as physical address, if the paging unit is disabled, otherwise; the paging unit converts the linear address into physical address.The paging unit is a memory management unit enabled only in protected mode. The paging mechanism allows handling of large segments of memory in terms of pages of 4Kbytesize. The paging unit operates under the control of segmentation unit. The paging unit if enabled converts linear addresses into physical addresses, in protected mode.

“Be yourself; everyone else is already taken.” ― Oscar Wilde

VIRTUAL 8086 MODE OF 80386DX

In its protected mode of operation, 80386DX provides a virtual 8086 operating environment to execute the 8086 programs. However, once the 80386 enters the protected mode from the real mode, it cannot return back to the real mode without a reset operation. The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086 real mode. In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in the 4Gbytes address space of the protected mode of 80386. Like 80386 real mode, the addresses in virtual8086 mode lie within 1Mbytes of memory. In virtual mode, the paging mechanism and protection capabilities are available at the service of the programmers (note that the 80386 supports multiprogramming, hence more than one programmer may use the CPU at a time).Paging unit may not be necessarily enabled in virtual mode, but may be needed to run the 8086 programs which require more than 1Mbyte of memory for memory management functions.In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each of the pages may be located anywhere within the maximum 4Gbytesphysical memory. The virtual mode allows the multiprogramming of 8086 applications. Figure 10.10 shows how the memory is managed in multitasking virtual 8086 environment.The virtual 8086 mode executes all the programs at privilege level-3. Any of the other programs may deny access to the virtual mode programs or data. However, the real mode programs are executed at the highest privilege level,Even in the virtual mode, all the interrupts and exceptions are handled by the protected, mode interrupt handler. To return to the protected mode from the virtual mode, any interrupt or exception may be used. As a part of interrupt service routine, the VM-bit may be reset to zero to pull back the 80386 into protected mode.Thus, the virtual 8086 mode of operation of 80386 offers an advantage of executing 8086 programs while in protected mode.

""Walking with a friend in the dark is better than walking alone in the light."" 

@Helen Keller

Architecture of 80387 processor

The 80387 has an 80-bit internal architecture that offers six to eleven times improvement in performance as compared to 80287. The architecture of 80387. The architecture and functional operation of 80387 is exactly similar to the 80287, except for the data bus size. The data bus of 80387 has 32 data lines D0-D31. The 80387 has two clock inputs to allow the possible asynchronous or synchronous operations with 80386. These operations are selected using the CKM pin of 80387. If CKM is high, the 80387 operates in synchronous mode, otherwise, it operates in asynchronous mode. The bus control unit of 80387 always operates synchronously with 80386, independent of the mode of operation of the floating point unit. In conjunction with READY input, the ADS input pin can be used to delay the bus cycles in reference to CPUCLK2 pin. The status enable pinacts as a chip select for the MCP 80387. The other pins of 80387 have similar functions as the corresponding pins of 80287. The data interface and control unit handle the data and direct into either FIFO or instruction decoder depending upon the bus control logic directive. The decoder decodes the instruction and derives the control signals to control the data flow inside the 80387. This unit generates the synchronization signals for 80386. The FPU is responsible for carrying out all the floating point calculations allotted to the coprocessor by 80387.

Love isn't something you find. Love is something that finds you. :::::@Loretta Young

ENHANCED INSTRUCTION SET OF A 80386 PROCESSOR

The instruction set of 80386 contains all the instructions supported by·80286. The 80286 instructions are designed to operate with 8-bit or 16-bit data, while the same mnemonics for 80386 instruction set may be executed over 32-bit operands, besides 8-bit and 16-bit operands.
The newly added instructions may be categorized into the following functional groups.
1. Bit scan instructions
2. Bit test instructions
3. Conditional set byte instructions
4. Shift double instructions
5. Control transfer via gates instructions.
1. Bit Scan Instructions: 80386 instruction set has two bit scan mnemonics, such as BSF (bit scan forward) and BSR (bit scan reverse). Both of these instructions scan the operand for a '1' bit, without actually rotating it. The BSF instruction scans the operand from right to left. If a '1' is encountered during the scan, zero flag is set and the bit position of '1' is stored into the destination operand. If no '1' is encountered, zero flag is reset. The BSR instruction also performs the same function but scans the source operand from the left most bit towards right.
2. Bit Test Instructions: 80386 have four bit test instructions, those are BT (test a bit), BTC (test a bit and complement), BTR (test and reset a bit) and BTS (test and set a bit). All these instructions test a bit position in the destination operand, specified by the source operand. If the bit position of the destination operand specified by the source operand satisfies the condition specified in the mnemonic, the carry flag is affected appropriately. For example, in the case of BT instruction, if the bit position in the destination operand, specified by the source operand, is '1', the carry flag is set, otherwise, it is cleared.
3. Conditional Set Byte instruction: This instruction sets all the operand bits, if the condition specified by the mnemonic is true. This instruction group has 16 mnemonics corresponding to 16 conditions as shown below.
E.g. SETO EAX; this instruction sets all the bits of EAX, if the overflow flag is set.
1. SETO Set on overflow
2. SETNO Set on no overflow
3. SETB/SETNAE Set on below/not above or equal
4. SETNB/SETAE Set on not below/above or equal
5. SETE/SETZ Set on equal/zero
6. SETNE/SETNZ Set on not equal/not zero
7. SETBE/SETNA Set on below or equal/not above
8. SETNBE/SETA Set on not below or equal/above
9. SETS Set on sign
10. SETNS Set on not sign
11. SETP/SETPE Set on parity/parity even
12. SETNP Set on not parity/parity odd
13. SETUSETNGE Set on less/not greater or equal
14. SETNUSET GE Set on not less/greater or equal
15. SETLE/SETNG Set on less or equal/not greater
16. SETNLE/SETG Set on not less or equal/greater
4. Shift Double Instructions: These instructions shift the specified number of bits from the source operand into the destination operand. The 80386 instruction set has two mnemonics under this category, such as SHLD (shift left double) and SHRD (shift right double). The SHLD instruction shifts the specified number of bits (in the instruction) from the upper side, i.e. MSB of the source operand into the lower side, i.e. LSB of the destination operand. The SHRD instruction shifts the number of bits specified in the instruction from the lower side, i.e. LSB of the source operand into the upper side, .i.e. MSB of the destination operand.
Ex: 1. SHLQ EAX, ECX, 5; This instruction shifts 5 MSB bits of ECX into the LSB positions of EAX one by one starting from the MSB of ECX. 2. SHRD EAX, ECX, 8; this instruction shifts 8 LSB bits of ECX into the MSB positions of EAX one by one starting from the LSB of ECX.
5. Control Transfer Instructions: The 80386 instruction set does not have any additional instructions for the intrasegment jump. However, for intersegment jumps, it has got a set of new instructions which are variations of the previous CALL and JUMP instructions, and are to be executed only in the protected mode. These instructions are used by 80386 to transfer the control either at the same privilege or at a different privilege level. Also, different versions of control transfer instructions are available to switch between the different task types and TSS (task state segment). The corresponding RET instructions are also available to switch back from the new task initiated via CALL, JMP or INT instructions to the parent task. Intel's 80387 has eight 80-bit floating point data registers, which are used to store signed 80-bit data in the form of exponent and significant. Each of these registers has a corresponding 2-bit tag field. The 80387 has a 16-bit control, status and tag word registers. The 80387 has two more 48-bit registers called as instruction and data pointers. The instruction and data pointer registers respectively point to the failing math coprocessor instruction and the corresponding numeric data, which is referred by the CPU. Two bits are allotted for each of the registers R0-R7 in the tag word. Also the tag bits can be used by the exception handlers to check the contents of a stack location without any manipulation. The status word represents the overall status of the coprocessor.
The 80387 can be configured by loading a control word from memory to its control word register. The control word register has exactly similar format as that of 80287.

You cannot believe in God until you believe in yourself.@VIVEKANADA

SEGMENTATION OF 80386 PROCESSOR

The memory management unit (MMU) consists of a segmentation unit and a paging unit. The
segmentation unit allows the use of two address components, such as segment and offset for relocabilityand sharing of code and data. The segmentation unit allows segments of size 4Gbytes at maximum. Thesegmentation unit provides a four level protection mechanism for protecting and isolating the system's code and data from those of the application program.
Descriptors
Every segment has a descriptor. When the programmer creates a logical segment, the system software
creates the corresponding descriptor with the help of compilers and loaders, linkers. It is the job of
operating system. Descriptors contain the information about segment. The 80386 descriptors have a 20- bit segment limit and 32-bit segment address. The descriptors of 80386 are 8-byte quantities containing access right or attribute bits along with the base and limit of the segments.
Descriptor Tables
In any system, there will be number of segments of various types created for various applications. Thus,there should be as many descriptors too. All these descriptors are stored in tables called descriptor tables. These tables are created by system software and stored in memory. The segmentation scheme provides a way of offering protection to different types of data and code.
Descriptor Attribute Bits

•  The A (accessed) attribute bit indicates whether the segment has been accessed by the CPU or not.
•  The TYPE field decides the descriptor type and hence the segment type.
•  The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor (S=1).
•  The DPL field specifies the descriptor privilege level.
•  The D bit specifies code segment operation size. If D=l, the segment is a 32-bitoperand segment,      else, it is a 16-bit operand segment.
•  The P-bit (present) signifies whether the segment is present in the physical memory or not. If P=l,    the segment is present in the physical memory.
•  The G (granularity) bit indicates whether the segment is page addressable. The zero-bit must remain  zero for compatibility with future processors.
•  The AVL (available) field specifies whether the descriptor is available for user or for the operating  system.

“Life is an exam where the syllabus is unknown and question papers are not set. Nor are there model answer papers.” ..@sudhamurty

DATA TYPES OF 80386 PROCESSOR

The 80386 supports the following  data types they are

•  Bit
•  Bit Field: A group of at the most 32 bits (4bytes)
•  Bit String: A string of contiguous bits of maximum 4Gbytes in length.
•  Signed Byte: Signed byte data
•  Unsigned Byte: Unsigned byte data.
•  Integer word: Signed 16-bit data.
•  Long Integer: 32-bit signed data represented in 2's complement form.
•  Unsigned Integer Word: Unsigned 16-bit data
•  Unsigned Long Integer: Unsigned 32-bit data
•  Signed Quad Word: A signed 64-bit data or four word data.
•  Unsigned Quad Word: An unsigned 64-bit data.
•  Offset: 16/32-bit displacement that points a memory location using any of the addressing modes.
•  Pointer: This consists of a pair of 16-bit selector and 16/32-bit offset.
•  Character: An ASCII equivalent to any of the alphanumeric or control characters.
•  Strings: These are the sequences of bytes, words or double words. A string may contain minimum one byte and maximum 4 Gigabytes.
• BCD: Decimal digits from 0-9 represented by unpacked bytes.
• Packed BCD: This represents two packed BCD digits using a byte, i.e. from 00 to 99.

'''Always bear in mind that your own resolution to succeed is more important than any other.'''@Abraham Lincoln

ADDRESSING MODES OF 80386 PROCESSORS

The 80386  addressing modes to facilitate efficient execution higher level language programs. The 80386 has all the addressing modes which were available with 80286. Besides these, 80386 have a family of scaled modes. In the case of scaled modes, any of the index register values can be multiplied by a valid scale factor to obtain the displacement. The valid scale factors are 1,2, 4, and 8. 1. Scaled Indexed Mode: The contents of an index register are multiplied by a scale factor that may be added further to get the operand offset. Ex. MOV EBX, LIST [ESI* 2] MUL ECX, LIST [EBP*4] 2. Based Scaled Indexed mode: The contents of an index register are multiplied by a scale factor and then added to base register to obtain the offset. Ex: MOV EBX, [EDX*4] [ECX] MOV EAX, [EBX*2] [ECX] 3. Based scaled indexed mode with displacement: the contents of an index register are multiplied by a scale factor and the result is added to a base register and a displacement to get the offset of an operand. Ex: MOV EAX, LIST [ESI* 2] [EBX+0800] MUL EBX, LIST [EDI*8] [ECX+0100].

''''''''''''''''Culture is the widening of the mind and of the spirit.''''''''

 @NEHRU

REGISTER ORGANISATION OF 80386 PROCESSORS

A. General Purpose Registers: The 80386 has eight 32-bit general purpose registers such as EAX, EBX, ECX, EDX, EBP, ESP, ESI and EDI which may be also used as either 8-bit or 16-bit registers. A 32-bit register, known as an extended register, is represented by the register name with prefix E.
B. Segment Registers and Instruction Pointer: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS. The CS and SS are the code and the stack segment registers respectively, while DS, ES, FS and GS are the four data segment registers. A 16-bit instruction pointer IP is available along with its 32-bit counterpart EIP.C. Flag Register: The flag register of 80386 is a 32-bit register. Out of the 32-bits, Intel has reserved bits D18 to D31, D15, D5 and D3, while D1 is always set at 1. The lower 15 bits (D0- D14) of this flag register are exactly the same as the 80286 flag registers. Only two extra new flags are added in to the flag register of 80386. These are the VM and RF flags.VM-Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception-13 is generated. This bit can be set using the IRET instruction or any task switch operation only in the protected mode.RF-Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for the IRET and POPF instructions. Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instructions causing a task switch. These instructions are used to set the RF to the value specified by the memory data available at the stack.D. Segment Descriptor Registers: The segment descriptor registers of 80386 are not available for programmers; they are internally used to store the descriptor information, like attributes, limit and base addresses of segments. The six segment registers have corresponding six 73-bit descriptor registers. Each of them contains 32-bit base address, 32-bit base limit and 9-bit attributes.E. Control Registers: The 80386 has three 32-bit control registers CR0, CR2 and CR3 to hold global machine status independent of the executed task. The load and store instructions are available to access these registers. The control register CR1 is reserved for use in future Intel processors.F. System Address and Segment Registers: Four special registers are used to refer the descriptor tables supported by 80386. The 80386 supports four types of descriptor tables such as global descriptor table (GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task state segment descriptor (TSS). The system address registers and system segment registers hold the addresses of these descriptor tables and the corresponding segments. These segments are named as GDTR, IDTR, LDTR and TR respectively. The GDTR and IDTR are called as system address and LDTR and TR are called as system segment registers.G. Debug and Test Registers: Intel has provided a set of eight debug registers for hardware debugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are Intel reserved. The initial four registers DR0 to DR3 store four program controllable break point addresses, while DR6 and DR7 respectively hold breakpoint status and break point control information. Two more test registers are provided by 80386 for page cacheing namely test control and test status registers.

Live as if you were to die tomorrow; learn as if you were to live forever.@M GANDHJI

String Manipulation Instructions of an processor

A series of data bytes or words available in memory at consecutive locations, to be referred to collectively or individually, are called as byte strings or word strings. For referring to a string, two parameters are required, starting or end address of the string and  length of the string. The length of a string is usually stored as count in CX register. The pointers and counters may be modified at each iteration, till the required condition for proceeding further is satisfied. The incrementing or decrementing of the pointer, in case of 8086 string instructions, depends upon the direction flag (DF) status. If it is a byte string operation, the index registers are updated (incrementing if DF is 0 or decrementing if DF is  by one. On the other hand, if it is a word string operation, the index registers are updated by two. The counter in both the cases is decremented by one. REP (Repeat Instruction Prefix): This instruction is used as a prefix to other instructions. The instruction to which the REP prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is automatically decremented by one). When CX becomes zero, the execution proceeds to the next instruction in sequence. There are two more options of the REP instruction. The first is REPE/REPZ, i.e. repeat operation while equal/zero. The second is REPNE/REPNZ allows for repeating the operation while not equal/not zero. These options are used for CMPS, SCAS instructions only, as instruction prefixes.MOVSB/MOVSW (Move String Byte or String Word): The MOVSB/MOVSW instruction moves a string of bytes/ words pointed to by DS: SI pair (source) to the memory location pointed to by ES: DI pair (destination). The REP instruction prefix is used with MOVS instruction to repeat it by a value given in the counter CX). The length of the byte string or word string must be stored in CX register. No flags are affected by this instruction.



 ==> Education is the most powerful weapon which you can use to change the world. 
@ Nelson Mandela

INSTRUCTION SET OF 8086/8088 processor

Data Copy/Transfer Instructions
               This type of instructions is used to transfer data from source operand to destination operand. All the store, move, load, exchange, input and output instructions belong to this category.1. MOV (Move): This data transfer instruction transfers data from one register/memory location to another register/memory location. The source may be any one of the segment registers or other general or special purpose registers or memory location or immediate data. The destination may register or memory location. However, in case of immediate addressing mode, a segment registercannot be a destination register. Note that both operands cannot be both memory locations. No flags are affected.
Ex. MOV AX, 5000H; Immediate AM
MOV AX, BX; Register AM
MOV AX, [SI]; Indirect AM
MOV AX, [2000H]; Direct AM
MOV AX, 5OH [BX]; Based relative, 50H Displacement
2. PUSH (Push to Stack): This instruction pushes the contents of the specified register/memory location onto the stack. The push operation decrements SP by two and then stores the contents of the operand onto the stack. The higher byte is pushed first and then the lower byte.
Ex. PUSH AX PUSH DS PUSH [5000H]; content of location 5000H and 5001H in DS are pushed onto the stack. 3. POP (Pop from Stack): This instruction when executed, loads the specified register/memory location with the contents of the memory location of which the address is formed using the current stack segment and stack pointer as usual. The stack pointer is incremented by 2. The POP instruction serves exactly opposite to the PUSH instruction. Ex. POP AX POP DS4. XCHG (Exchange): This instruction exchanges the contents of the specified source and destination operands, which may be registers or one of them may be a memory location. EX. XCHG [5000H], AX; exchanges data between AX and a memory location [5000H]5. IN (Input the port): This instruction is used for reading an input port. The address of the input port may be specified in the instruction directly or indirectly. AL and AX are the allowed destinations for 8 and 16-bit input operations. DX is the only register (implicit) which is allowed to carry the port address.EX. IN AL, 0300H; reads data from an 8-bit port whose address is 0300H and stores it in AL. IN AX, DX; reads data from a 16-bit port whose address is in DX and stores it in AX. 6. OUT (Output to the Port): This instruction is used for writing to an output port. The address of the output port may be specified in the instruction directly or implicitly in DX. Contents of AX or AL are transferred to a directly or indirectly addressed port after execution of this instruction.EX. OUT 0300H, AL; this sends data available in AL to a port whose address is 0300H.OUT DX, AX; this sends data in AX to a port whose address is specified implicitly in DX.7. LEA (Load Effective Address): This instruction loads the offset of an operand in the specified register. Ex. LEA BX, ADR; loads the offset of the label ADR in BX.8. LDS/LES (Load Pointer to DS/ES): The instruction, Load DS/ES with pointer, loads the DS or ES register and the specified destination register in the instruction with the content of memory location specified as source in the instruction.

"""A leader is one who knows the way, goes the way, and shows the way""".  

 @John C. Maxwell

QUEUE OPERATION OF AN PROCESSOR

At the starting the CS: IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty and the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS: IP address is odd or two bytes at a time, if the CS: IP address is even. The first byte is a complete opcode in case of some instructions (one byte opcode instruction) and it is a part of opcode, in case of other instructions (two byte long opcode instructions), the remaining part of opcode may lie in the second byte. But invariably the first byte of an instruction is an opcode. These opcodes along with data are fetched and arranged in the queue. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is updated. The microprocessor does not perform the next fetch operation till at least two bytes of the instruction queue are emptied. The instruction execution cycle is never broken for fetch operation. After decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte. If it is single opcode byte, the next bytes are treated as data byte depending upon the decoded instruction length; otherwise, the next byte in the queue is treated as the second byte of the instruction opcode. The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.The next byte after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program. The main point to be noted here is that the fetch operation of the next instruction is overlapped with the execution of the current instruction. As shown in the architecture, there are two separate units, namely, execution unit and bus interface unit. While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.RQ GT0 , RQ GT1-Request/Grant: These pins are used by other local bus masters, in maximum mode, to force the processor to release the local bus at the end of the processor's current bus cycle. Each of the pins is bidirectional with RQ GT0 having higher priority than RQ GT1. RQ GT Pins have internal pull-up resistors and may be left unconnected.

""""++THE BEST BRAINS OF THE NATION MAY BE FOUND ON THE LAST BENCHES OF THE CLASSROOM++"""
              ===@ Abdul kalam @=====
                           

Architecture of 8088 proccesor

The register set of 8088 is exactly the same as in to 8086. The architecture of 8088 is also
similar to 8086 except for two changes; a) 8088 has 4-byte instruction queue and b) 8088
has 8-bit data bus. Figure 1.14 shows the 8088 architecture.The addressing capability of 8088 is 1Mbyte; therefore, it needs 20 address bits, i.e. 20 addressing lines. While handling this 20-bit address, the segmented memory scheme is used and the complete physical address forming procedure is the same as explained in case of 8086.While physically interfacing memory to 8088, there is nothing like an even address bank or odd address bank. The complete memory is homogeneously addressed as a bank of 1Mbyte memory locations using the segmented memory scheme.
The 8088 can access only a byte at a time. This reduces the speed of operation of 8088 as compared to 8086, but the 8088 can process the 16-bit data internallyAD7-AD0 (Address/Data): These lines are the time multiplexed address/data bus. During T1 the bus is used for conducting addresses and during T2, T3, Tw and T4 states these lines are used for transferring data. These are moved to high impedance state (tristated) during 'hold acknowledge' and 'interrupt acknowledge' cycles. A15-A8 (Address Bus): These lines provide the address bits A8 to A15 in the entire bus cycle. These
need not be latched for obtaining a stable valid address. These are active high and are tnstated
during the acknowledge cycles. Note that, as the 8088 data bus is only of 8 bits there is no need of
the BHE signal. SS0: A new pin SS0 is introduced in 8088 instead of BHE pin in 8086. In minimum mode, the pin SS0 is logically equivalent to the So in maximum mode. IO M : This pin is similar to M IO pin of 8086, but it offers an 8085 compatible, memory/IO bus interface. The signals SS0,DT R, IO M can be decoded to interpret the activities of the microprocessor.

---------The best preparation for tomorrow is doing your best today. -------------

@------ H.Jackson Brown---@

THE PROCESSOR 8088

 The microprocessor 8088 has all the programming facilities that 8086 has, along with some

hardware features of 8086 like 1Mbyte memory addressing capability, operating modes (MN MX ), interrupt structure etc. However 8088 has 8-bit data bus. This feature of 8088 makes the circuits, designed around 8085, compatible with 8088. All the peripheral interfacing schemes with 8088 are the same as those for the 8-bit processors. The memory and I/0 addressing schemes are now exactly similar to 8085 schemes except for the increased memory (1Mbyte).

-----The best and most beatiful things in the world cannot be seen or ever touched -they must be felt with the heart ------ 
----@Helen Keller@---

I/O ADDRESSING CAPABILITY

 The 8086/8088 processor can address up to 64K byte I/O registers or 32K word registers. The I/O address appears on the address lines A0 to A15 for one clock cycle (T1). It may then be latched using the ALE signal. The upper address lines (A16 - A19) are at logic 0 level during the I/O operations.
The 16-bitregister DX is used as 16-bit I/O address pointer, with full capability to address up to 64K devices. In memory mapped I/O interfacing, the I/O device addresses are treated as memory locations in page 0, i.e. segment address 0000H.Even addressed bytes are transferred on D7-Do and odd addressed bytes are transferred on D8-D15 lines.
 

*********One of the most beautiful qualities of true friendship is to understand and to be understood.***** #@Lucius Annaeus Seneca

GENERAL BUS OPERATION

 The 8086 has a combined address and data bus commonly referred to as a time multiplexed

address and data bus. The main reason behind multiplexing address and data over the same
pins is the maximum utilization of processor pins and it facilitates the use of 40 pin
standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, whenever required.Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3 and T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle. During T2, i.e. the next cycle, the bus is tristated foranging the direction of bus for the following data read cycle. The data transfer takes place during T3 and T4.In case, an addressed device is slow and shows 'NOT READY' status the wait states Tw are inserted between T3 and T4. These clock states during wait period are called idle states (T),wait states (Tw) or inactive states. The processor uses these cycles for internal housekeeping.The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN MX input. The negative edge of this ALE pulse is used to separate the address and the data or In maximum mode, the status lines S0, Sl and S2 are used to indicate the type of operation.Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.Address is valid during T1 while the status bits S3 to S7 are valid during T2 through T4.

______The best way out is always through.______
@----Robert Frost----@

MAXIMUM MODE 8086 SYSTEM AND TIMINGS

In the maximum mode, the 8086 is operated by connecting the MN MX pin to ground. In
this mode, the processor derives the status signals S2 , S1 and S0 . Another chip called bus
controller derives the control signals using this status information.In the maximum mode, there may be more than one microprocessor in the system configuration. The other components in the system are the same as in the minimum mode system.The basic functions of the bus controller chip IC8288, is to derive control signals like RD and WR (for memory and I/O devices), DEN , DT R , ALE, etc. using the information made available by the processor on the status lines.The bus controller chip has input lines S2 , S1 , S0 and CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN , DT R,MRDC ,MWTC, AMWC ,IORC , IOWC and AIOWC . The AEN , IOB and CEN pins are specially useful for multiprocessor systems. AEN and IOB are generally grounded. CEN pin is usually lied to +5V. The significance of the MCE PDEN output depends upon the status of the IOB pin.If IOB is grounded, it acts as master cascade enable to control cascaded 8259A, else it acts
as peripheral data enable used in the multiple bus configurations. INTApin is used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC , IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the addressed port. The MRDC , MWTC are memory read command and memory write command signals respectively and may be used as memory read and write signals. All these command signals instruct the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available. They also serve the same purpose, but are activated one clock cycle earlier than the IOWCand MWTC signals, respectively. The maximum mode system is  The maximum mode system timing diagrams are also divided in two portions as read (input) and write (output) timing diagrams. The address/data and address/status timings are similar to the minimum mode. ALE is asserted in T1, just like minimum mode. The only difference lies in the status signals used and the available control and advanced command signals. Maximum mode timings for the read operation while same for the write operation.

$$$$$$ Yesterday is not ours to recover, but tomorrow is ours to win or lose.$$$$$$  @Lyndon B. Johnson

SIGNAL DESCRIPTIONS OF 8086

 SIGNAL DESCRIPTIONS OF 8086
 The microprocessor 8086 is a 16-bit CPU available in three clock rates, i.e. 5, 8 and 10 MHz, packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configurations to achieve high performance.  Some of the pins serve a particular function in minimum mode (single processor mode) and others function in maximum mode (multiprocessor mode) configuration. The 8086 signals can be categorized in three groups. The first are the signals having common functions in minimum as well as maximum mode, the second are the signals which have special functions for ·minimum mode and the third are the signals having special functions for maximum mode.The following signal descriptions are common for both the minimum and maximum modes: AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is a wait state. These lines are active high and enter into high impedance state (float to a tristate) during interrupt acknowledge and local bus hold acknowledge cycles.A19-A16/S6-S3: These are the time multiplexed address and status lines. During T1, these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations; status information is available on those lines for T2, T3, Tw and T4. The S4 and S3 pins indicate which segment registers is represently being used for memory accesses . These lines enter into high impedance state (float to a tristate) during the local bus hold acknowledge. The status line S6 is always low (logical). The address bits are separated from the status bits using latches controlled by the ale signal.

^^^^^^Do not dwell in the past, do not dream of the future, concentrate the mind on the present moment.^^^^@ Buddha

MEMORY SEGMENTATION

The memory in an 8086/8088 based system is organized as segmented memory. In this scheme, the complete physically available memory may be divided into a number of logical segments. Each segment is 64K bytes in size and is addressed by one of the segment registers. The 16-bit contents of the segment register actually point to the starting location of a particular segment.To address aspecific memory location within a segment, we need an offset address. The offset address is also 16-bit long so that the maximum offset value can be FFFFH, and the maximum size of any segment is thus 64K locations.The CPU 8086 is able to address 1Mbytes of physical memory. The complete 1Mbyte memory can be divided into 16 segments, each of 64Kbytes size. The addresses of the segments (segment base address) may be assigned as 0000H to F000H respectively. The offset address values are from 0000H to FFFFH so that the physical addresses range from 00000H to FFFFFH. In the above case, the segments are called non-overlapping segments. The non-overlapping segments are  in some cases, however, the segments may be overlapping as  Suppose a segment starts at a particular address and its maximum size can be 64Kbytes. But, if another segment starts before this 64Kbytes location of the first segment, the two segments are said to be overlapping segments. The area of memory from the start of the second segment to the possible end of the first segment is called as overlapped segment area.

+++++Love isn't something you find.                  Love is something that finds you.+++++ @ Loretta Young

ARCHITECTURE OF 8086 PROCESSOR

It supports a 16-bit ALU, a set of 16-bit registers and provides segmented memory addressing capability, a rich instruction set, powerful interrupt structure, fetched instruction queue for overlapped fetching and execution etc. The complete architecture of 8086 can be divided into two parts (a) Bus Interface Unit (BIU) and (b) Execution Unit (EU).
 BUS INTERFACE UNIT (BIU)
The bus interface unit contains the circuit for physical address calculations and a pre-decoding instruction byte queue (6 bytes long). The bus interface unit makes the system bus signals available for external interfacing of the devices. In other words, this unit isresponsible for establishing communications with external devices and peripherals including memory via the bus.The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is generated using segment and offset registers, each 16-bit long. register also called as segment address is shifted left bit-wise four times and to this result, content of an offset register also called as offset address is added to produce a 20-bit physical address. For example, if the segment address is 1005H and the offset is 5555H, then the physical address is calculated as below. Thus the segment addressed by the segment value 1005H can have offset values from 0000H to FFFFH within it, i.e. maximum 64K locations may be accommodated in the segment. Since the offset is a 16-bit number, each segment can have a maximum of 64K locations. The bus interface unit has a separate adder to perform this procedure for obtaining a physical address while addressing memory. The segment address value is to be taken from an appropriate segment register depending upon whether code, data or stack are to be accessed, while the offset may be the content of IP, BX, SI, DI,SP or an immediate 16-bit value, depending upon the addressing mode. In case of 8085, once the opcode is fetched and decoded, the external bus remains free for some time, while the processor internally executes the instruction.

 This time slot is utilized in 8086 to achieve the overlapped fetch and execution cycles. While the fetched instruction is executed internally, the external bus is used to fetch the machine code of the next instruction and arrange it in a queue called as prefetched instruction byte queue. It is a 6 bytes long, first-in first-out structure. The instructions from the queue are taken for decoding sequentially. Once a byte is decoded, the queue is rearranged by pushing it out and the queue status is checked for the possibility of the next opcode fetch cycle. While the opcode is fetched by the bus interface unit (BIU), the execution unit (EU) executes the previously decoded instruction concurrently. The BIU along with the execution unit (EU) thus forms a pipeline. The bus interface unit thus manages the complete interface of execution unit with memory and I/0 devices, of course, under the control of the timing and control unit.
EXECUTION UNIT (EU)
The execution unit contains the register set of 8086 except segment registers and IP. It has a 16-bit ALU, able to perform arithmetic and logic operations. The 16-bit flag register reflects the results of execution by the ALU. The decoding unit decodes the opcode bytes issued from the instruction byte queue. The timing and control unit derives the necessary control signals to execute the instruction opcode received from the queue, depending upon the information made available by the decoding circuit. The execution unit may pass the results to the bus interface unit for storing them in memory.

----The most important thing is to enjoy your life - to be happy - it's all that matters.----
@Audrey Hepburn

Register Organization of 8086 Microprocessor

The 8086 has a powerful set of registers. It includes general purpose registers, segment registers, pointers and index registers and flag register.  All the registers of 8086 are 16-bit registers.

General Data Registers

The registers AX, BX, CX and DX are the general purpose 16-bit registers.AX is used as 16-bit accumulator, with the lower 8-bits of AX designated as AL and higher 8-bits as AH. AL can be used as an 8-bit accumulator for 8-bit operations. This is the most important general purpose register having multiple functions.The register BX is used as offset storage for forming physical addresses in case of certain addressing modes.The register CX is also used as a default counter in case of string and loop instructions.DX register is a general purpose register which may be used as an implicit operand or destination in case of a few instructions.

Segment Registers

 Unlike 8085, the 8086 addresses a segmented memory. The complete 1 megabyte memory is divided into 16 logical segments. Each segment thus contains 64 Kbytes of memory.There are four segment registers such as Code Segment Register (CS), Data Segment Register (DS), Extra Segment Register (ES) and Stack Segment Register (SS).Generally segment register is used to store the upper 16-bits of the starting address of a particular segment. The contents of the segment register are called segment base address.The code segment register is used for addressing a memory location in the code segment of the memory, where the executable program is stored.Similarly, the data segment register points to the data segment of the memory, where the data is stored.The extra segment also refers to a segment which essentially is another data segment of the memory. Thus the extra segment also contains data.

 The stack segment register is used for addressing stack segment of memory. The stack segment is that segment of memory which is used to store stack data. The CPU uses the stack for temporarily storing important data, e.g. the contents of the CPU registers which will be required at a later stage

 While addressing any location in the memory bank, the physical address is calculated from two parts, the first is segment address and the second is offset.The segment registers contain 16-bit segment base addresses, related to different segments. Any of the pointers and index registers or BX may contain the offset of the location to be addressed.Thus the CS, DS, SS and ES segment registers respectively contain the segment addresses for the code, data, stack and extra segments of memory.

 Pointers and Index Registers

The pointers contain offset within the particular segments. The pointers IP, BP and SP usually contain offsets within the code, data and stack segments respectively.The index registers are used as general purpose registers as well as for offset storage in case of indexed, based indexed and relative based indexed addressing modes.The register SI is generally used to store the offset of source data in data segment while the register DI is used to store the offset of destination in data or extra segment. The index registers are particularly useful for string manipulations.

 Flag Register

 8086 has a 16-bit flag register which is divided into two parts such as (a) conditional code or status flags and (b) machine control flags. The flag register of 8086 the condition code flag register is the lower byte of the 16-bit flag register along with the overflow flag. These flag registers of 8086 reflects the results of the operations performed by ALU.The control flag register is the higher byte of the flag register of 8086. It contains three flags such as direction flag (D), interrupt flag (I) and trap flag (T).

The description of each flag bit is as follows:

S-Sign Flag: This flag is set, when the result of any computation is negative. For signed computations, the sign flag equals the MSB of the result.

Z-Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous instruction/instructions is zero.

P-Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1s.

C-Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or borrow in case of subtraction.

T-Trap Flag: If this flag is set, the processor enters the single step execution mode. In other words, a trap interrupt is generated after execution of each instruction. The processor executes the current instruction and the control is transferred to the Trap interrupt service routine.

I-interrupt Flag: If this flag is set, the maskable interrupts are recognized by the CPU, otherwise, they are ignored.

D-Direction Flag: This is used by string manipulation instructions. If this flag bit is. '0', the string is processed beginning from the lowest address to the highest address, i.e. auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e. auto decrementing mode.

AC-Auxiliary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e. bit three, during addition or borrow for the lowest nibble, i.e. bit three, during subtraction.

O-Overflow Flag: This flag is set, if an overflow occurs, i.e. if the result of a signed operation is large enough to be accommodated in a destination register. For example, in case of the addition of two signed numbers, if the result overflows into the sign bit, i.e. the result is of more than 7-bits in size in case of 8-bit signed operations and more than15-bits in size in case of 16-bit signed operations, and then the overflow flag will be set.

_____We are all here on earth to help others; 

                       what on earth the others are here for I don't know.______ 

@W. H. Auden

8086 MICROPROCESSOR

In 1978, Intel developed 8086 processor. The Intel 8086 is a 16-bit microprocessor, implemented in N-channel, depletion mode, silicon gate technology (HMOS), and packaged it in a 40-pin dual in line package. Salient features of 8086 microprocessor are:It is a 16-bit microprocessor. It has a 20 bit address bus. So it can access up to 220 or 10, 48,576 memory locations (1 MB).It is a 40 pin dual in line package.It can support up to 64K I/O ports.It provides fourteen16 -bit registers.It has multiplexed address and data bus AD0- AD15 and A16 – A19.It requires single phase clock with 33% duty cycle to provide internal timing.It is designed to operate in two modes, Minimum and Maximum modes.

It can prefetches up to 6 instruction bytes from memory and store them in order to speed up instruction execution.It requires +5V power supply.

------Good, better, best. Never let it rest.'Til your good is better and your better is best.---- @St. Jerome