GENERAL BUS OPERATION

 The 8086 has a combined address and data bus commonly referred to as a time multiplexed

address and data bus. The main reason behind multiplexing address and data over the same
pins is the maximum utilization of processor pins and it facilitates the use of 40 pin
standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, whenever required.Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3 and T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle. During T2, i.e. the next cycle, the bus is tristated foranging the direction of bus for the following data read cycle. The data transfer takes place during T3 and T4.In case, an addressed device is slow and shows 'NOT READY' status the wait states Tw are inserted between T3 and T4. These clock states during wait period are called idle states (T),wait states (Tw) or inactive states. The processor uses these cycles for internal housekeeping.The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN MX input. The negative edge of this ALE pulse is used to separate the address and the data or In maximum mode, the status lines S0, Sl and S2 are used to indicate the type of operation.Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.Address is valid during T1 while the status bits S3 to S7 are valid during T2 through T4.

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