REGISTER ORGANISATION OF 80386 PROCESSORS

A. General Purpose Registers: The 80386 has eight 32-bit general purpose registers such as EAX, EBX, ECX, EDX, EBP, ESP, ESI and EDI which may be also used as either 8-bit or 16-bit registers. A 32-bit register, known as an extended register, is represented by the register name with prefix E.
B. Segment Registers and Instruction Pointer: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS. The CS and SS are the code and the stack segment registers respectively, while DS, ES, FS and GS are the four data segment registers. A 16-bit instruction pointer IP is available along with its 32-bit counterpart EIP.C. Flag Register: The flag register of 80386 is a 32-bit register. Out of the 32-bits, Intel has reserved bits D18 to D31, D15, D5 and D3, while D1 is always set at 1. The lower 15 bits (D0- D14) of this flag register are exactly the same as the 80286 flag registers. Only two extra new flags are added in to the flag register of 80386. These are the VM and RF flags.VM-Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception-13 is generated. This bit can be set using the IRET instruction or any task switch operation only in the protected mode.RF-Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for the IRET and POPF instructions. Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instructions causing a task switch. These instructions are used to set the RF to the value specified by the memory data available at the stack.D. Segment Descriptor Registers: The segment descriptor registers of 80386 are not available for programmers; they are internally used to store the descriptor information, like attributes, limit and base addresses of segments. The six segment registers have corresponding six 73-bit descriptor registers. Each of them contains 32-bit base address, 32-bit base limit and 9-bit attributes.E. Control Registers: The 80386 has three 32-bit control registers CR0, CR2 and CR3 to hold global machine status independent of the executed task. The load and store instructions are available to access these registers. The control register CR1 is reserved for use in future Intel processors.F. System Address and Segment Registers: Four special registers are used to refer the descriptor tables supported by 80386. The 80386 supports four types of descriptor tables such as global descriptor table (GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task state segment descriptor (TSS). The system address registers and system segment registers hold the addresses of these descriptor tables and the corresponding segments. These segments are named as GDTR, IDTR, LDTR and TR respectively. The GDTR and IDTR are called as system address and LDTR and TR are called as system segment registers.G. Debug and Test Registers: Intel has provided a set of eight debug registers for hardware debugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are Intel reserved. The initial four registers DR0 to DR3 store four program controllable break point addresses, while DR6 and DR7 respectively hold breakpoint status and break point control information. Two more test registers are provided by 80386 for page cacheing namely test control and test status registers.

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