Architecture of 8088 proccesor

The register set of 8088 is exactly the same as in to 8086. The architecture of 8088 is also
similar to 8086 except for two changes; a) 8088 has 4-byte instruction queue and b) 8088
has 8-bit data bus. Figure 1.14 shows the 8088 architecture.The addressing capability of 8088 is 1Mbyte; therefore, it needs 20 address bits, i.e. 20 addressing lines. While handling this 20-bit address, the segmented memory scheme is used and the complete physical address forming procedure is the same as explained in case of 8086.While physically interfacing memory to 8088, there is nothing like an even address bank or odd address bank. The complete memory is homogeneously addressed as a bank of 1Mbyte memory locations using the segmented memory scheme.
The 8088 can access only a byte at a time. This reduces the speed of operation of 8088 as compared to 8086, but the 8088 can process the 16-bit data internallyAD7-AD0 (Address/Data): These lines are the time multiplexed address/data bus. During T1 the bus is used for conducting addresses and during T2, T3, Tw and T4 states these lines are used for transferring data. These are moved to high impedance state (tristated) during 'hold acknowledge' and 'interrupt acknowledge' cycles. A15-A8 (Address Bus): These lines provide the address bits A8 to A15 in the entire bus cycle. These
need not be latched for obtaining a stable valid address. These are active high and are tnstated
during the acknowledge cycles. Note that, as the 8088 data bus is only of 8 bits there is no need of
the BHE signal. SS0: A new pin SS0 is introduced in 8088 instead of BHE pin in 8086. In minimum mode, the pin SS0 is logically equivalent to the So in maximum mode. IO M : This pin is similar to M IO pin of 8086, but it offers an 8085 compatible, memory/IO bus interface. The signals SS0,DT R, IO M can be decoded to interpret the activities of the microprocessor.

---------The best preparation for tomorrow is doing your best today. -------------

@------ H.Jackson Brown---@