PROTECTED MODE OF 80386

All the capabilities of 80386 are available for utilization in its protected mode of operation. In protected mode, it can address 4 Gigabytes of physical memory and 64 Terabytes of virtual memory per task.The 80386 in protected mode supports all the software’s (programs) written for 80286 and 8086 to be executed under the control of memory management and protection abilities of 80386.The 80386 in protected mode supports all the software’s (programs) written for 80286 and 8086 to be executed under the control of memory management and protection abilities of 80386.In this mode, the contents of segment registers are used as selectors to address descriptors which contain the segment limit, base address and access rights byte of the segment. The effective address (offset) is added with segment base address to calculate linear address. This linear address is further used as physical address, if the paging unit is disabled, otherwise; the paging unit converts the linear address into physical address.The paging unit is a memory management unit enabled only in protected mode. The paging mechanism allows handling of large segments of memory in terms of pages of 4Kbytesize. The paging unit operates under the control of segmentation unit. The paging unit if enabled converts linear addresses into physical addresses, in protected mode.

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VIRTUAL 8086 MODE OF 80386DX

In its protected mode of operation, 80386DX provides a virtual 8086 operating environment to execute the 8086 programs. However, once the 80386 enters the protected mode from the real mode, it cannot return back to the real mode without a reset operation. The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086 real mode. In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in the 4Gbytes address space of the protected mode of 80386. Like 80386 real mode, the addresses in virtual8086 mode lie within 1Mbytes of memory. In virtual mode, the paging mechanism and protection capabilities are available at the service of the programmers (note that the 80386 supports multiprogramming, hence more than one programmer may use the CPU at a time).Paging unit may not be necessarily enabled in virtual mode, but may be needed to run the 8086 programs which require more than 1Mbyte of memory for memory management functions.In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each of the pages may be located anywhere within the maximum 4Gbytesphysical memory. The virtual mode allows the multiprogramming of 8086 applications. Figure 10.10 shows how the memory is managed in multitasking virtual 8086 environment.The virtual 8086 mode executes all the programs at privilege level-3. Any of the other programs may deny access to the virtual mode programs or data. However, the real mode programs are executed at the highest privilege level,Even in the virtual mode, all the interrupts and exceptions are handled by the protected, mode interrupt handler. To return to the protected mode from the virtual mode, any interrupt or exception may be used. As a part of interrupt service routine, the VM-bit may be reset to zero to pull back the 80386 into protected mode.Thus, the virtual 8086 mode of operation of 80386 offers an advantage of executing 8086 programs while in protected mode.

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Architecture of 80387 processor

The 80387 has an 80-bit internal architecture that offers six to eleven times improvement in performance as compared to 80287. The architecture of 80387. The architecture and functional operation of 80387 is exactly similar to the 80287, except for the data bus size. The data bus of 80387 has 32 data lines D0-D31. The 80387 has two clock inputs to allow the possible asynchronous or synchronous operations with 80386. These operations are selected using the CKM pin of 80387. If CKM is high, the 80387 operates in synchronous mode, otherwise, it operates in asynchronous mode. The bus control unit of 80387 always operates synchronously with 80386, independent of the mode of operation of the floating point unit. In conjunction with READY input, the ADS input pin can be used to delay the bus cycles in reference to CPUCLK2 pin. The status enable pinacts as a chip select for the MCP 80387. The other pins of 80387 have similar functions as the corresponding pins of 80287. The data interface and control unit handle the data and direct into either FIFO or instruction decoder depending upon the bus control logic directive. The decoder decodes the instruction and derives the control signals to control the data flow inside the 80387. This unit generates the synchronization signals for 80386. The FPU is responsible for carrying out all the floating point calculations allotted to the coprocessor by 80387.

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ENHANCED INSTRUCTION SET OF A 80386 PROCESSOR

The instruction set of 80386 contains all the instructions supported by·80286. The 80286 instructions are designed to operate with 8-bit or 16-bit data, while the same mnemonics for 80386 instruction set may be executed over 32-bit operands, besides 8-bit and 16-bit operands.
The newly added instructions may be categorized into the following functional groups.
1. Bit scan instructions
2. Bit test instructions
3. Conditional set byte instructions
4. Shift double instructions
5. Control transfer via gates instructions.
1. Bit Scan Instructions: 80386 instruction set has two bit scan mnemonics, such as BSF (bit scan forward) and BSR (bit scan reverse). Both of these instructions scan the operand for a '1' bit, without actually rotating it. The BSF instruction scans the operand from right to left. If a '1' is encountered during the scan, zero flag is set and the bit position of '1' is stored into the destination operand. If no '1' is encountered, zero flag is reset. The BSR instruction also performs the same function but scans the source operand from the left most bit towards right.
2. Bit Test Instructions: 80386 have four bit test instructions, those are BT (test a bit), BTC (test a bit and complement), BTR (test and reset a bit) and BTS (test and set a bit). All these instructions test a bit position in the destination operand, specified by the source operand. If the bit position of the destination operand specified by the source operand satisfies the condition specified in the mnemonic, the carry flag is affected appropriately. For example, in the case of BT instruction, if the bit position in the destination operand, specified by the source operand, is '1', the carry flag is set, otherwise, it is cleared.
3. Conditional Set Byte instruction: This instruction sets all the operand bits, if the condition specified by the mnemonic is true. This instruction group has 16 mnemonics corresponding to 16 conditions as shown below.
E.g. SETO EAX; this instruction sets all the bits of EAX, if the overflow flag is set.
1. SETO Set on overflow
2. SETNO Set on no overflow
3. SETB/SETNAE Set on below/not above or equal
4. SETNB/SETAE Set on not below/above or equal
5. SETE/SETZ Set on equal/zero
6. SETNE/SETNZ Set on not equal/not zero
7. SETBE/SETNA Set on below or equal/not above
8. SETNBE/SETA Set on not below or equal/above
9. SETS Set on sign
10. SETNS Set on not sign
11. SETP/SETPE Set on parity/parity even
12. SETNP Set on not parity/parity odd
13. SETUSETNGE Set on less/not greater or equal
14. SETNUSET GE Set on not less/greater or equal
15. SETLE/SETNG Set on less or equal/not greater
16. SETNLE/SETG Set on not less or equal/greater
4. Shift Double Instructions: These instructions shift the specified number of bits from the source operand into the destination operand. The 80386 instruction set has two mnemonics under this category, such as SHLD (shift left double) and SHRD (shift right double). The SHLD instruction shifts the specified number of bits (in the instruction) from the upper side, i.e. MSB of the source operand into the lower side, i.e. LSB of the destination operand. The SHRD instruction shifts the number of bits specified in the instruction from the lower side, i.e. LSB of the source operand into the upper side, .i.e. MSB of the destination operand.
Ex: 1. SHLQ EAX, ECX, 5; This instruction shifts 5 MSB bits of ECX into the LSB positions of EAX one by one starting from the MSB of ECX. 2. SHRD EAX, ECX, 8; this instruction shifts 8 LSB bits of ECX into the MSB positions of EAX one by one starting from the LSB of ECX.
5. Control Transfer Instructions: The 80386 instruction set does not have any additional instructions for the intrasegment jump. However, for intersegment jumps, it has got a set of new instructions which are variations of the previous CALL and JUMP instructions, and are to be executed only in the protected mode. These instructions are used by 80386 to transfer the control either at the same privilege or at a different privilege level. Also, different versions of control transfer instructions are available to switch between the different task types and TSS (task state segment). The corresponding RET instructions are also available to switch back from the new task initiated via CALL, JMP or INT instructions to the parent task. Intel's 80387 has eight 80-bit floating point data registers, which are used to store signed 80-bit data in the form of exponent and significant. Each of these registers has a corresponding 2-bit tag field. The 80387 has a 16-bit control, status and tag word registers. The 80387 has two more 48-bit registers called as instruction and data pointers. The instruction and data pointer registers respectively point to the failing math coprocessor instruction and the corresponding numeric data, which is referred by the CPU. Two bits are allotted for each of the registers R0-R7 in the tag word. Also the tag bits can be used by the exception handlers to check the contents of a stack location without any manipulation. The status word represents the overall status of the coprocessor.
The 80387 can be configured by loading a control word from memory to its control word register. The control word register has exactly similar format as that of 80287.

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SEGMENTATION OF 80386 PROCESSOR

The memory management unit (MMU) consists of a segmentation unit and a paging unit. The
segmentation unit allows the use of two address components, such as segment and offset for relocabilityand sharing of code and data. The segmentation unit allows segments of size 4Gbytes at maximum. Thesegmentation unit provides a four level protection mechanism for protecting and isolating the system's code and data from those of the application program.
Descriptors
Every segment has a descriptor. When the programmer creates a logical segment, the system software
creates the corresponding descriptor with the help of compilers and loaders, linkers. It is the job of
operating system. Descriptors contain the information about segment. The 80386 descriptors have a 20- bit segment limit and 32-bit segment address. The descriptors of 80386 are 8-byte quantities containing access right or attribute bits along with the base and limit of the segments.
Descriptor Tables
In any system, there will be number of segments of various types created for various applications. Thus,there should be as many descriptors too. All these descriptors are stored in tables called descriptor tables. These tables are created by system software and stored in memory. The segmentation scheme provides a way of offering protection to different types of data and code.
Descriptor Attribute Bits

•  The A (accessed) attribute bit indicates whether the segment has been accessed by the CPU or not.
•  The TYPE field decides the descriptor type and hence the segment type.
•  The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor (S=1).
•  The DPL field specifies the descriptor privilege level.
•  The D bit specifies code segment operation size. If D=l, the segment is a 32-bitoperand segment,      else, it is a 16-bit operand segment.
•  The P-bit (present) signifies whether the segment is present in the physical memory or not. If P=l,    the segment is present in the physical memory.
•  The G (granularity) bit indicates whether the segment is page addressable. The zero-bit must remain  zero for compatibility with future processors.
•  The AVL (available) field specifies whether the descriptor is available for user or for the operating  system.

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DATA TYPES OF 80386 PROCESSOR

The 80386 supports the following  data types they are

•  Bit
•  Bit Field: A group of at the most 32 bits (4bytes)
•  Bit String: A string of contiguous bits of maximum 4Gbytes in length.
•  Signed Byte: Signed byte data
•  Unsigned Byte: Unsigned byte data.
•  Integer word: Signed 16-bit data.
•  Long Integer: 32-bit signed data represented in 2's complement form.
•  Unsigned Integer Word: Unsigned 16-bit data
•  Unsigned Long Integer: Unsigned 32-bit data
•  Signed Quad Word: A signed 64-bit data or four word data.
•  Unsigned Quad Word: An unsigned 64-bit data.
•  Offset: 16/32-bit displacement that points a memory location using any of the addressing modes.
•  Pointer: This consists of a pair of 16-bit selector and 16/32-bit offset.
•  Character: An ASCII equivalent to any of the alphanumeric or control characters.
•  Strings: These are the sequences of bytes, words or double words. A string may contain minimum one byte and maximum 4 Gigabytes.
• BCD: Decimal digits from 0-9 represented by unpacked bytes.
• Packed BCD: This represents two packed BCD digits using a byte, i.e. from 00 to 99.

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ADDRESSING MODES OF 80386 PROCESSORS

The 80386  addressing modes to facilitate efficient execution higher level language programs. The 80386 has all the addressing modes which were available with 80286. Besides these, 80386 have a family of scaled modes. In the case of scaled modes, any of the index register values can be multiplied by a valid scale factor to obtain the displacement. The valid scale factors are 1,2, 4, and 8. 1. Scaled Indexed Mode: The contents of an index register are multiplied by a scale factor that may be added further to get the operand offset. Ex. MOV EBX, LIST [ESI* 2] MUL ECX, LIST [EBP*4] 2. Based Scaled Indexed mode: The contents of an index register are multiplied by a scale factor and then added to base register to obtain the offset. Ex: MOV EBX, [EDX*4] [ECX] MOV EAX, [EBX*2] [ECX] 3. Based scaled indexed mode with displacement: the contents of an index register are multiplied by a scale factor and the result is added to a base register and a displacement to get the offset of an operand. Ex: MOV EAX, LIST [ESI* 2] [EBX+0800] MUL EBX, LIST [EDI*8] [ECX+0100].

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